Digi NS9750 manuales

Digi NS9750 Manual de usuario (898 paginas)

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Tabla de contenidos

NS9750 Hardware Reference

Contents

........................394

Using This Guide

What’s in this guide

Related documentation

Documentation updates

Customer support

About NS9750

NS9750 Features

System Boot

PCI/CardBus port

Flexible LCD controller

USB ports

Serial ports

Vector interrupt controller

System timers

General purpose I/O

External interrupts

Clock generator

System-level interfaces

System boot

RESET_DONE as an input

RESET_DONE as an output

System clock

Figure 4: System clock

USB clock

NS9750 Pinout

System Memory interface

Ethernet interface

Clock generation/system pins

PCI interface

Table 8: PCI interface pinout

PCI/CardBus signals

GPIO MUX

Table 10: GPIO MUX pinout

USB Power

Controller

LCD module signals

C interface

USB interface

Power ground

About the processor

Instruction sets

ARM instruction set

Thumb instruction set

Java instruction set

ARM926EJ-S system addresses

Accessing CP15 registers

Terms and abbreviations

VINITHI signal is high

BIGENDINIT signal is high

Table 20: R0: ID code

Dsize and Isize fields

R1: Control register

R4 register

R5: Fault Status registers

31 0987 43

UNP/SBZ Domain Status

R6: Fault Address register

R7: Cache Operations register

Rd for the CP15 R7 MCR

R8:TLB Operations register

R9: Cache Lockdown register

MRC p15, 0, Rn, c9, c0, 1 ;

ORR Rn, Rn, 0x01 ;

MCR p15, 0, Rn, c9, c0, 1 ;

R10: TLB Lockdown register

R11 and R12 registers

R13: Process ID register

MRC p15,0,Rd,c13,c0,1

100

MCR p15,0,Rd,c13,c0,1

100

Jazelle (Java)

101

Memory Management Unit (MMU)

102

Working with the CPU

103

Address translation

105

31 014 13

106

Translation table base

106

Modified virtual address

108

SHOULD BE ZERO

109

Section descriptor

110

Large Small Tiny Description

114

[15:12] --- [9:6]

114

MMU faults and CPU aborts

119

MCR p15,0,Rd,c7,c13,1)

121

Domain access control

122

Fault checking sequence

123

External aborts

126

Enabling the MMU

127

Disabling the MMU

128

TLB structure

128

Caches and write buffer

129

Write buffer

130

Enabling the caches

131

Cache MVA and Set/Way formats

133

ARM926EJ-S S NSETS

134

4 KB 5 32

134

8 KB 6 64

134

16 KB 7 128

134

associativity

135

Self-modifying code

136

AHB behavior

136

Instruction Memory Barrier

137

Sample IMB sequences

138

Memory Controller

139

Features

140

System overview

141

Low-power operation

142

Memory map

142

– boot_strap[4:3]

143

– gpio[49]

143

Static memory controller

145

Write protection

146

Extended wait transfers

146

Memory mapped peripherals

147

Static memory initialization

147

WA ITR D= 2)

150

WA IT RD ). Table 51

150

WA IT RD =0 )

152

Figure 44

153

WA IT RD

155

WA IT RD cycles. Subsequent

157

WAITPAGE cycles. The

157

WAI TTUR N field can

167

Figure 54

170

Figure 55

172

Byte lane control

173

Address connectivity

174

Dynamic memory controller

186

Address mapping

187

ADDROUT)

188

SDRAM (BRC) devices

199

(RBC) devices

209

Registers

226

Reset values

228

Control register

229

Table 138: Control register

230

Status register

231

Configuration register

231

233

SREFREQ)

234

13121110987654321015 14

235

Reserved

235

REFRESHReserved

235

CLKDELAY (command

236

Reserved RP

237

Reserved RAS

238

Reserved SREX

239

Reserved APR

240

Reserved DAL

241

Reserved WR

242

Reserved RC

243

Reserved RFC

244

Reserved XSR

245

0x1–0x3FF

248

CLK frequency = 50 MHz

249

(16 x 10

249

x 50 x 10

249

/ 16) - 1 = 49

249

Table 157: Address mapping

250

Examples

252

System Control Module

277

Bus interconnection

278

System bus arbiter

278

Master Write Mux

279

Slave Read Mux

279

Address decoding

285

is active high

286

Table 167 shows the

286

assignments for NS9750

286

Programmable timers

287

Interrupt controller

291

System attributes

295

Bootstrap initialization

296

Table 169 shows

297

multiplier values

297

Timer 0–15 Read register

309

ISRADDR register

312

Interrupt Status Active

313

Interrupt Status Raw

314

Address: A090 0170

315

Address: A090 0174

315

Clock Configuration register

317

Address: A090 0180

319

Address: A090 0184

320

PLL Configuration register

323

Timer 0–15 Control registers

325

Address: A090 01D0 / 01D4

327

Gen ID register

335

Ethernet Communication

339

Overview

340

Ethernet MAC

341

 MCS: MAC control sublayer

342

 TFUN: Transmit function

342

 RFUN: Receive function

342

(enet_phy_int)

343

Station address logic (SAL)

345

Statistics module

345

AUTOZ is set to 1

346

Ethernet front-end module

347

Receive packet processor

348

Ethernet Communication Module

349

31 151630 29 28

350

Transmit packet processor

351

Ethernet Slave Interface

354

Interrupts

355

Table 204: Reset control

356

External CAM filtering

358

RXD[1:0]

360

RX_WR logic

364

Address: A060 0008

368

Address: A060 0018

368

Address: A060 001C

371

MAC Configuration Register #1

372

D00 R/W RXEN 0 Receive enable

374

MAC Configuration Register #2

375

0x55 and is error-free

376

Address: A060 0408

378

Maximum Frame register

381

PHY Support register

382

Clocks field settings

384

Station Address registers

388

390

Address: A060 0504

391

Address: A060 0508

391

Statistics registers

392

Receive statistics counters

393

Transmit statistics counters

397

(NON_VLAN) or 1522

400

Carry Register 1

402

Table 232: Carry Register 1

402

Carry Register 2

403

Table 233: Carry Register 2

403

Address: A060 073C

406

Address: A060 0A10

409

Address: A060 0A14

411

Address: A060 0A28

415

RX Free Buffer register

419

TX buffer descriptor RAM

420

Sample hash table code

421

PCI-to-AHB Bridge

427

About the PCI-to-AHB Bridge

428

Transaction ordering

434

Endian configuration

435

Configuration registers

435

FUNCTION_NUMBER

436

REGISTER_NUMBER

436

REGISTER_NUMBER field in the

437

Table 255: Command register

438

PCI Status register

439

REVISION_ID field in the PCI

440

CLASS_CODE field in the PCI

440

0x0. As

441

PCI bus arbiter

442

Slave interface

444

Address: A030 0000

447

Address: A030 0004

448

Address: A030 0008

449

Address: A030 000C

450

PCI Configuration 0 register

452

Address: A030 0014

453

Address: A030 0018

454

Address: A030 001C

455

Address: A030 0020

456

Address: A030 0024

457

Address: A030 0028

457

Address: A030 002C

458

Address: A030 0030

459

Address: A030 0034

461

Address: A030 0038

462

Address: A030 003C

463

Address: A030 0040

463

Address: A030 0044

464

Address: A030 0048

465

Address: A030 004C

466

CardBus Socket Event register

470

CardBus Socket Mask register

471

Address: A030 1008

472

BAD_VCC_REQ

474

Address: A030 100C

475

Address: A030 1010

478

PCI system configurations

480

External

481

PCI Arbiter

481

PCI interrupts

482

CardBus Support

485

CardBus adapter requirements

488

CardBus interrupts

489

BBus Bridge

491

BBus bridge functions

492

Bridge control logic

493

DMA accesses

495

BBus control logic

496

Cycles and BBus arbitration

497

DMA buffer descriptor

498

Descriptor list processing

500

Peripheral DMA read access

501

Peripheral DMA write access

502

Peripheral REQ signaling

503

Design Limitations

504

Interrupt aggregation

507

Bandwidth requirements

507

SPI-EEPROM boot logic

508

Time = (1 / freq) * EEPROM

509

 Burst type: Sequential

511

 OpMode: Standard

511

SDRAM boot algorithm

512

Address: A040 0000 / 0020

515

Address: A040 0004 / 0024

515

Address: A040 0008 / 0028

518

Address: A040 000C / 002C

520

Address: A040 1004

523

BBus DMA Controller

525

DMA context memory

527

DMA channel assignments

533

DMA Buffer Descriptor Pointer

536

DMA Control register

538

BBus Utility

545

0x9060 0000

546

Master Reset register

547

GPIO Configuration registers

548

Address: 9060 0020

549

Address: 9060 001C

550

Address: 9060 0018

550

Address: 9060 0014

551

Address: 9060 0010

552

GPIO Control registers

553

GPIO Control Register #1

554

GPIO Status registers

556

GPIO Status Register #1

557

BBus Monitor register

559

BBus DMA controller

560

USB Configuration register

562

Endian Configuration register

563

ARM Wake-up register

565

C Master/Slave Interface

567

C external addresses

569

C command interface

569

Locked interrupt driven mode

570

C registers

571

Address: 9050 0000

572

Status Receive Data register

573

Master Address register

574

Slave Address register

575

Interrupt Codes

577

Software driver

579

Flow charts

580

S_RX_DATA_1ST

581

S_TX_DATA_1ST

581

LCD Controller

583

LCD features

584

LCD panel resolution

585

LCD panel support

585

Number of colors

586

Table 343: CLCDCLK selection

589

Signals and interrupts

590

AHB interface

592

Pixel serializer

593

RAM palette

597

Grayscaler

598

Panel clock generator

598

Timing controller

598

Generating interrupts

599

CLSTN[0]

600

MLSTN[0]

600

CUSTN[0]

601

LCDTiming0

604

CLCDCLK/3)

605

CLCDCLK/7)

605

LCDTiming1

606

LCDTiming2 register

607

CLCP from

610

CLCP = CLCDCLK/(PCD+2)

610

LCDTiming3

611

LCDUPBASE and LCDLPBASE

611

0x00000000

612

LCDINTRENABLE

613

LCDControl register

614

LCDStatus register

617

LCDInterrupt register

618

LCDUPCURR and LCDLPCURR

618

LCDPalette register

619

Serial Control Module: UART

625

Bit-rate generator

627

UART mode

628

FIFO management

629

Receive FIFO interface

630

0x11 being read last

631

Serial port performance

632

. Table 366

634

Address: 9020 0004 / 0044

638

9030 0004 / 0044

638

Address: 9020 0008 / 0048

641

9030 0008 / 0048

641

0x13. The

651

Address: 9020 0010 / 0050

653

9030 0010 / 0050

653

Address: 9020 0014 / 0054

654

9030 0014 / 0054

654

Address: 9020 0018 / 0058

656

9030 0018 / 0058

656

Address: 9020 0020 / 0060

659

9030 0020 / 0060

659

Serial Control Module: SPI

667

SPI mode

670

. Table 383

675

Address: 9020 000C / 004C

684

9030 000C / 004C

684

Channel Status Register A

690

IEEE 1284 Peripheral

693

Requirements

694

Compatibility mode

695

Nibble mode

696

Byte mode

696

ECP mode

697

Data and command FIFOs

699

IEEE 1284 negotiation

700

BBus slave and DMA interface

701

Address: 9040 0004

705

FIFO Status register

708

Both registers are 32 bits

711

Address: 9040 0024

713

Address: 9040 0028

714

Printer Data Pins register

715

Port Status register, host

716

Port Control register

717

Feature Control Register A

718

Feature Control Register B

719

Interrupt Enable register

719

Master Enable register

721

Extended Control register

722

Interrupt Status register

723

Pin Interrupt Mask register

724

Granularity Count register

726

Forward Address register

727

Warning:

729

USB Controller Module

731

USB module architecture

732

USB device block

734

Packet and data flow

735

Host block

736

Packet data flow

737

USB device endpoint

738

Transmission error handling

738

Handling USB-IN packet errors

739

USB block registers

740

USB Global registers

740

Address: 9010 0000

741

Address: 9010 0004

742

Address: 9010 0010

745

Address: 9010 0014

748

USB host block registers

749

HCRevision register

750

HcControl register

751

Table 424: HcControl register

752

HcCommandStatus register

754

HcInterruptStatus register

757

HcInterruptEnable register

759

HcInterruptDisable register

761

HcHCCA register

763

HcPeriodCurrentED register

764

HcControlHeadED register

765

HcControlCurrentED register

766

HcBulkHeadED register

767

HcBulkCurrentED register

768

HcDoneHead register

770

HcFmInterval register

771

HcFmRemaining register

772

HcFmNumber register

773

HcPeriodicStart register

774

HcLsThreshold register

775

Root hub partition registers

776

HcRhDescriptorA register

777

HcRhDescriptorB register

779

HcRhStatus register

780

HcRhPortStatus[1] register

783

 In global switching mode

785

USB Device Block registers

789

Device endpoint status

794

Address: 9010 3000

795

Address: 9010 3010

795

Address: 9010 3020

797

Address: 9010 3030

799

Address: 9010 3004

800

Address: 9010 3014

801

Address: 9010 3024

802

Address: 9010 3034

803

FIFO Packet Control registers

804

CHAPTER 17

811

Electrical characteristics

812

Maximum power dissipation

813

Typical power dissipation

813

DC electrical characteristics

814

USB DC electrical outputs

815

Power sequencing

818

Memory timing

819

SDRAM burst read (16-bit)

820

This is the CAS address

821

SDRAM burst write (16-bit)

822

SDRAM burst read (32-bit)

823

SDRAM burst write (32-bit)

825

SDRAM load mode

826

SDRAM refresh mode

827

Clock enable timing

827

WTRD = 1

829

WTRD = 2

830

WTRD = from 1 to 15

831

WTWR = 0

832

Static RAM write cycle

833

Note-5Note-4

834

Ethernet timing

837

Ethernet MII timing

838

Ethernet RMII timing

839

PCI timing

840

Internal PCI arbiter timing

842

PCI clock timing

844

C timing

845

LCD timing

846

LCD output timing

850

SPI timing

851

4 ±5% duty cycle skew

852

5 ±10% duty cycle skew

852

(see note 7)

853

IEEE 1284 timing

855

USB timing

856

USB differential data timing

857

USB full speed load timing

857

USB low speed load

858

R2 reset_n to reset_done 4 ms

859

JTAG timing

860

Clock timing

861

LCD input clock timing

862

System PLL bypass mode timing

863

Packaging

865

Figure 149: NS9750 top view

866

NS9750, 352 BGA

868

Product specifications

869

Numerics

871

I- Index-3

873

BBus peripheral address

875

See BBus DMA

875

DMA memory-to

876

DMA peripheral-to

876

Ethernet front-end

877

FIQ interrupts

878

I- Index-9

879

Index-10

880

Index-11

881

Index-12

882

Index-13

883

Index-14

884

Index-16

886

Index-17

887

Index-18

888

Index-19

889

Index-20

890

Index-21

891

Index-22

892

Index-23

893

Index-24

894

Index-25

895

Index-26

896

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Digi NS9750 manuales

Digi NS9750 Manual de usuario (898 paginas)

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