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PCI/CardBus signals
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23
Notes:
1 Add external pulldown resistor or drive with the NS9750B-A1 only if the PCI interface is not being used.
Figure 5, "NS9750B-A1 unused PCI termination," shows which signals can be driven by the
NS9750B-A1 and which signals require pullups or pulldowns.
2 Add external pullup resistors regardless of whether the PCI interface is being used.
3 Add external pullup resistor only if the PCI interface is not being used.
4 Add external pullup resistor in CardBus mode.
5 Add external pulldown resistor in CardBus mode.
6 Add external pullup only if the PCI interface is being used and this signal is also being used.
INTB# CCLKRUN#
4
Bidir CardBus pin used to negotiate with the
external CardBus device before stopping the
clock.
Allows external CardBus device to request
that the clock be restarted.
INTC# CSTSCHG
5
Input CardBus status change interrupt signal.
GNT1# CGNT#
4
Output Grant to external CardBus device from
NS9750B-A1’s internal arbiter.
GNT2# CVS1 Output Voltage sense pin. Normally driven low by
NS9750B-A1, but toggled during interrogation
of the external CardBus device to find voltage
requirements.
Note:
Do not connect directly to the
CardBus connector. See the diagram
“CardBus system connections to
NS9750B-A1” in the NS9750B-A1
Hardware Reference.
GNT3# CVS2 Output Voltage sense pin. Normally driven low by
NS9750B-A1, but toggled during interrogation
of the external CardBus device to find voltage
requirements.
REQ1# CREQ#
4
Input Request from external CardBus device to
NS9750B-A1’s internal arbiter.
REQ2# CCD1
4
Input Card detect pin. Pulled up when the socket is
empty and pulled low when the external
CardBus device is in the socket.
REQ3# CCD2
4
Input Card detect pin. Pulled up when the socket is
empty and pulled low when the external
CardBus device is in the socket.
PCI signal CardBus signal CardBus type Description
Table 11: CardBus IO muxed signals
- NS9750B-A1 Datasheet 1
- Contents 3
- NS9750B-A1 Datasheet 03/2006 4
- NS9750B-A1 Features 5
- 2 6
- System-level interfaces 8
- System configuration 9
- Table 2: PLL ND[4:0] 10
- Pin name Configuration bits 10
- General Purpose ID register 11
- System boot 12
- System Clock 13
- NS9750B-A1 14
- USB clock 15
- System Memory interface 16
- Pin # Signal Name 17
- I/O Description 17
- Name I/O Description 20
- Ethernet interface 22
- Clock generation/system pins 23
- PCI interface 24
- PCI/CardBus signals 26
- 24 28
- GPIO MUX 29
- Pin # Signal name 30
- Table 12: GPIO MUX pinout 30
- USB Power 35
- Controller 35
- CLSTN[0] 36
- MLSTN[0] 36
- CUSTN[0] 37
- RED[0] 38
- GREEN[0], BLUE[0] 38
- C interface 39
- USB Interface 39
- Reserved pins 41
- Address and register maps 42
- BBus peripheral address map 43
- Electrical characteristics 44
- Maximum power dissipation 45
- Typical power dissipation 45
- DC electrical characteristics 46
- USB DC electrical outputs 47
- 44 48
- Power sequencing 49
- Memory timing 50
- SDRAM burst read (16-bit) 51
- SDRAM burst write (16-bit) 52
- SDRAM burst read (32-bit) 52
- SDRAM burst write (32-bit) 53
- SDRAM load mode 54
- SDRAM refresh mode 54
- Clock enable timing 54
- SRAM timing 55
- 52 56
- WTWR = from 0 to 15 60
- 57 61
- 58 62
- Ethernet timing 63
- Ethernet MII timing 64
- Ethernet RMII timing 64
- PCI timing 65
- Internal PCI arbiter timing 66
- 64 68
- C timing 69
- LCD timing 70
- 68 72
- LCD output timing 73
- SPI timing 74
- 72 76
- IEEE 1284 timing 77
- USB timing 78
- USB full speed load 79
- USB low speed load 79
- 80
- JTAG timing 81
- Clock timing 82
- 79 83
- Packaging 84
- NS9750B-A1, 388 BGA 86
- Product specifications 87
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