
PCI timing
62
NS9750B-A1 Datasheet 03/2006
Notes:
1 Minimum times are specified with 0pf and maximum times are specified with 30pf.
2 pci_clk_out high and low times specified as 50% of the clock period ±1 ns.
Internal PCI arbiter timing
Parameter Description Min Max Units Notes
P1 pci_clk_in to signal valid delay 2 10 ns 1
P2 input setup to pci_clk_in 5 ns 1
P3 input hold from pci_clk_in 0 ns
P4 pci_clk_in to signal active 2 ns 1
P5 pci_clk_in to signal float 28 ns 1
P6 pci_clk_out high time 50%-1 50%+1 ns 2
P7 pci_clk_out low time 50%-1 50%+1 ns 2
P8 pci_clk_in cycle time 30 ns
P9 pci_clk_in high time 11 ns
P10 pci_clk_in low time 11 ns
Table 31: CardBus timing characteristics
data0 addr
P1
P2
P3
Master 1 CycleMaster 1 CycleMaster 2 CycleMaster 2 CycleMaster 1 CycleMaster 1 Cycle
Switch MasterSwitch Master
addr data1 data2 data0 addr data0
pci_clk_in
frame_n
irdy_n
ad[31:0]
pci_arb_req_1_n
pci_arb_req_2_n
pci_arb_gnt_1_n
pci_arb_gnt_2_n
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